1016 search results - page 74 / 204 » Test Generation for Designs with On-Chip Clock Generators |
APAQS
2001
IEEE
13 years 11 months ago
2001
IEEE
Integration testing has always been a challenge especially if the system under test is large with many subsystems and interfaces. This paper proposes an approach to design End-toE...
HASE
2002
IEEE
14 years 22 days ago
2002
IEEE
Components (in-house or pre-fabricated) are increasingly being used to reduce the cost of software development. Given that these components may not have not been developed with de...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
ICST
2009
IEEE
14 years 2 months ago
2009
IEEE
It is challenging to test applications and functions for which the correct output for arbitrary input cannot be known in advance, e.g. some computational science or machine learni...
ET
2002
13 years 7 months ago
2002
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CASBUS that solves ...