1016 search results - page 77 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ERSA
2010
13 years 5 months ago
2010
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
DAC
1996
ACM
13 years 12 months ago
1996
ACM
The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined. The addition of variance mismatched signals is identified as a testi...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
- Extension of a BIST design algorithm is proposed in this paper. The method is based on a synthesis of a combinational block - the decoder, transforming pseudo-random code words i...
QSIC
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper proposes a stochastic voting for testing a large number of Web Services (WS) under group testing. In the future, a large number of WS will be available and they need to...
FUIN
2008
13 years 7 months ago
2008
We study runtime distributions of subsumption testing. On graph data randomly sampled from two different generative models we observe a gradual growth of the tails of the distribut...