1016 search results - page 87 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ESANN
2003
13 years 10 months ago
2003
- A test bed of experiments with real and artificially generated data has been designed to compare the performance of three well-known algorithms for BSS. The main goal of these ex...
DAC
2009
ACM
14 years 10 months ago
2009
ACM
The discrepancy between integrated circuits' activities in normal functional mode and that in structural test mode has an increasing adverse impact on the effectiveness of ma...
IJAIT
2000
13 years 8 months ago
2000
Knowledge-based engineering and computational intelligence are expected to become core technologies in the design and manufacturing for the next generation of space exploration mi...
DAC
2007
ACM
14 years 10 months ago
2007
ACM
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
TCAD
2008
13 years 9 months ago
2008
Abstract--A key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques ...