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» Test Pattern Generation Under Low Power Constraints
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VTS
1995
IEEE
94views Hardware» more  VTS 1995»
13 years 11 months ago
Synthesis of locally exhaustive test pattern generators
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...
Günter Kemnitz
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 12 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ICCD
2006
IEEE
127views Hardware» more  ICCD 2006»
14 years 4 months ago
Power Droop Testing
Circuit activity is a function of input patterns. When circuit activity changes abruptly, it can cause sudden drop or rise in power supply voltage. This change is known as power d...
Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd...
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
13 years 11 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
TCBB
2010
98views more  TCBB 2010»
13 years 2 months ago
VARUN: Discovering Extensible Motifs under Saturation Constraints
Abstract-The discovery of motifs in biosequences is frequently torn between the rigidity of the model on the one hand and the abundance of candidates on the other. In particular, m...
Alberto Apostolico, Matteo Comin, Laxmi Parida