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» Test Resource Partitioning and Optimization for SOC Designs
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EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
14 years 22 days ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
14 years 1 months ago
Optimal buffered routing path constructions for single and multiple clock domain systems
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
FPL
2000
Springer
130views Hardware» more  FPL 2000»
14 years 6 days ago
Area-Optimized Technology Mapping for Hybrid FPGAs
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation h...
Srini Krishnamoorthy, Sriram Swaminathan, Russell ...
AAAI
2012
11 years 11 months ago
Optimizing Payments in Dominant-Strategy Mechanisms for Multi-Parameter Domains
In AI research, mechanism design is typically used to allocate tasks and resources to agents holding private information about their values for possible allocations. In this conte...
Lachlan Thomas Dufton, Victor Naroditskiy, Maria P...
GECCO
2006
Springer
206views Optimization» more  GECCO 2006»
14 years 7 days ago
A dynamically constrained genetic algorithm for hardware-software partitioning
In this article, we describe the application of an enhanced genetic algorithm to the problem of hardware-software codesign. Starting from a source code written in a high-level lan...
Pierre-André Mudry, Guillaume Zufferey, Gia...