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» Test generation in VLSI circuits for crosstalk noise
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FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
14 years 28 days ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
GLVLSI
2002
IEEE
136views VLSI» more  GLVLSI 2002»
14 years 18 days ago
Test generation for resistive opens in CMOS
This paper develops new techniques for detecting both stuck-open faults and resistive open faults, which result in increased delays along some paths. The improved detection of CMO...
Arun Krishnamachary, Jacob A. Abraham
SBCCI
2003
ACM
160views VLSI» more  SBCCI 2003»
14 years 27 days ago
Novel Design Methodology for High-Performance XOR-XNOR Circuit Design
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi
CEC
2005
IEEE
14 years 1 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
VLSID
2003
IEEE
96views VLSI» more  VLSID 2003»
14 years 8 months ago
Design Of A Universal BIST (UBIST) Structure
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...