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» Test generation in VLSI circuits for crosstalk noise
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ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
13 years 11 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
VLSID
2005
IEEE
120views VLSI» more  VLSID 2005»
14 years 1 months ago
On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattachar...
VLSI
2007
Springer
14 years 1 months ago
Impact of hardware emulation on the verification quality improvement
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
Youssef Serrestou, Vincent Beroulle, Chantal Robac...
VLSID
1998
IEEE
117views VLSI» more  VLSID 1998»
13 years 12 months ago
Partial Scan Selection Based on Dynamic Reachability and Observability Information
A partial scan selection strategy is proposed in which flip-flops are selected via newly proposed dynamic reachability and observability measures such that the remaining hard-to-d...
Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. R...
SBCCI
2005
ACM
86views VLSI» more  SBCCI 2005»
14 years 1 months ago
Ultra-low power CMOS cells for temperature sensors
Temperature sensors and voltage references require cells that generate both PTAT (Proportional To Absolute Temperature) and NTC (Negative Temperature Coefficient) voltages. We pre...
Conrado Rossi, Pablo Aguirre