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» Test generation in VLSI circuits for crosstalk noise
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TNN
2008
95views more  TNN 2008»
13 years 7 months ago
Minimizing the Effect of Process Mismatch in a Neuromorphic System Using Spike-Timing-Dependent Adaptation
Abstract--This paper investigates whether spike-timing-dependent plasticity (STDP) can minimize the effect of mismatch within the context of a depth-from-motion algorithm. To impro...
Katherine Cameron, Alan Murray
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 8 months ago
Impact of NBTI on FPGAs
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
Krishnan Ramakrishnan, S. Suresh, Narayanan Vijayk...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 1 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
14 years 27 days ago
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim...
DAC
2000
ACM
13 years 12 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas