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» Testing in the Component Age
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DFT
2007
IEEE
104views VLSI» more  DFT 2007»
14 years 4 months ago
Reduction of Fault Latency in Sequential Circuits by using Decomposition
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky
DATE
2005
IEEE
204views Hardware» more  DATE 2005»
14 years 3 months ago
Evaluation of Error-Resilience for Reliable Compression of Test Data
This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an Automatic Test Equipment (ATE) to the...
Hamidreza Hashempour, Luca Schiano, Fabrizio Lomba...
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
14 years 2 months ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
CDC
2008
IEEE
114views Control Systems» more  CDC 2008»
13 years 11 months ago
Dynamic test selection for reconfigurable diagnosis
Abstract-- Detecting and isolating multiple faults is a computationally intense task which typically consists of computing a set of tests, and then computing the diagnoses based on...
Mattias Krysander, Fredrik Heintz, Jacob Roll, Eri...
ESOP
2006
Springer
14 years 1 months ago
Types for Dynamic Reconfiguration
We define a core language combining computational and architectural primitives, and study how static typing may be used to ensure safety properties of component composition and dyn...
João Costa Seco, Luís Caires