We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
Generating test data for formal state based specifications is computationally expensive. This paper improves a framework that addresses this issue by representing the test data ge...
Karnig Derderian, Mercedes G. Merayo, Robert M. Hi...
Undersea localization requires a computationally expensive partial differential equation simulation to test each candidate hypothesis location via matched filter. We propose a met...
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
— Quasirandom or low discrepancy sequences, such as the Van der Corput, Sobol, Faure, Halton (named after their inventors) etc. are less random than a pseudorandom number sequenc...