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ISCAS
2005
IEEE
153views Hardware» more  ISCAS 2005»
14 years 3 months ago
A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
Paris Kitsos, Michalis D. Galanis, Odysseas G. Kou...
IJNSEC
2010
144views more  IJNSEC 2010»
13 years 4 months ago
A Note On Self-Shrinking Lagged Fibonacci Generator
Lagged Fibonacci Generators (LFG) are used as a building block of key-streamgenerator in stream cipher cryptography. In this note we have used the self-shrinkingconcept in LFG and ...
Moon K. Chetry, W. B. Vasantha Kandaswamy
ISPEC
2011
Springer
13 years 28 days ago
Meet-in-the-Middle Attack on 8 Rounds of the AES Block Cipher under 192 Key Bits
The AES block cipher has a 128-bit block length and a user key of 128, 192 or 256 bits, released by NIST for data encryption in the USA; it became an ISO international standard in ...
Yongzhuang Wei, Jiqiang Lu, Yupu Hu
ISCAS
2008
IEEE
127views Hardware» more  ISCAS 2008»
14 years 4 months ago
Compact ASIC implementation of the ICEBERG block cipher with concurrent error detection
— ICEBERG is a block cipher that has been recently proposed for security applications requiring efficient FPGA implementations. In this paper, we investigate a compact ASIC imple...
Huiju Cheng, Howard M. Heys
ITC
2003
IEEE
157views Hardware» more  ITC 2003»
14 years 3 months ago
Parity-Based Concurrent Error Detection in Symmetric Block Ciphers
Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurren...
Ramesh Karri, Grigori Kuznetsov, Michael Göss...