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EUROPDS
1997
13 years 8 months ago
A Combined Virtual Shared Memory and Network which Schedules
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
Ronald Moore, Bernd Klauer, Klaus Waldschmidt
DAC
2007
ACM
14 years 8 months ago
Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
Pramod Chandraiah, Rainer Dömer
BMVC
2002
13 years 9 months ago
Improving architectural 3D reconstruction by plane and edge constraining
This paper presents new techniques for improving the structural quality of automatically acquired architectural 3D models. Common architectural features like parallelism and ortho...
H. Cantzler, Robert B. Fisher, Michel Devy
ICMCS
2007
IEEE
144views Multimedia» more  ICMCS 2007»
14 years 1 months ago
A Framework for Modular Signal Processing Systems with High-Performance Requirements
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
Lukas Diduch, Ronald Müller, Gerhard Rigoll
IFIPPACT
1994
13 years 8 months ago
Exploiting the Parallelism Exposed by Partial Evaluation
: We describe an approach to parallel compilation that seeks to harness the vast amount of ne-grain parallelism that is exposed through partial evaluation of numerically-intensive ...
Rajeev J. Surati, Andrew A. Berlin