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ASAP
1996
IEEE
145views Hardware» more  ASAP 1996»
13 years 11 months ago
A Synthesis System For Bus-Based Wavefront Array Architectures
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
Reiner W. Hartenstein, Jürgen Becker, Michael...
LPNMR
2009
Springer
14 years 2 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
POPL
2009
ACM
14 years 8 months ago
The theory of deadlock avoidance via discrete control
Deadlock in multithreaded programs is an increasingly important problem as ubiquitous multicore architectures force parallelization upon an ever wider range of software. This pape...
Manjunath Kudlur, Scott A. Mahlke, Stéphane...
CCGRID
2005
IEEE
14 years 1 months ago
Using semantic Web technology to automate data integration in grid and Web service architectures
While the Grid and Web Services have helped us support heterogeneous resource access through the use of service oriented architectures, they have not addressed the issue of hetero...
Martin Szomszor, Terry R. Payne, Luc Moreau
DAMON
2009
Springer
14 years 2 months ago
Frequent itemset mining on graphics processors
We present two efficient Apriori implementations of Frequent Itemset Mining (FIM) that utilize new-generation graphics processing units (GPUs). Our implementations take advantage ...
Wenbin Fang, Mian Lu, Xiangye Xiao, Bingsheng He, ...