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ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 1 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
IPPS
2008
IEEE
14 years 2 months ago
Programmability of the HPCS Languages: A case study with a quantum chemistry kernel
As high-end computer systems present users with rapidly increasing numbers of processors, possibly also incorporating attached co-processors, programmers are increasingly challeng...
Aniruddha G. Shet, Wael R. Elwasif, Robert J. Harr...
IFIP12
2004
13 years 9 months ago
Model-Based Debugging with High-Level Observations
Recent years have seen considerable developments in modeling techniques for automatic fault location in programs. However, much of this research considered the models from a standa...
Wolfgang Mayer, Markus Stumptner
DAC
2002
ACM
14 years 8 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
ECAI
2004
Springer
14 years 1 months ago
High-Level Observations in Java Debugging
Recent years have seen considerable developments in modeling techniques for automatic fault location in programs. However, much of this research considered the models from a standa...
Wolfgang Mayer, Markus Stumptner