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» The Case for a Single-Chip Multiprocessor
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ASAP
2006
IEEE
130views Hardware» more  ASAP 2006»
14 years 2 months ago
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Data-Pipelining is a widely used model to represent streaming applications. Incremental decomposition and optimization of a data-pipelining application onto a multi-processor plat...
Bo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, ...
ICPADS
2006
IEEE
14 years 2 months ago
Accuracy versus Migration Overhead in Real-Time Multiprocessor Reweighting Algorithms
We consider schemes for enacting task share changes—a process called reweighting—on real-time multiprocessor platforms. Our particular focus is reweighting schemes that are de...
Aaron Block, James H. Anderson
DATE
2010
IEEE
159views Hardware» more  DATE 2010»
14 years 1 months ago
A rapid prototyping system for error-resilient multi-processor systems-on-chip
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
Matthias May, Norbert Wehn, Abdelmajid Bouajila, J...
IPPS
1998
IEEE
14 years 22 days ago
Fault-Tolerant Message Routing for Multiprocessors
In this paper the problem of fault-tolerant message routing in two-dimensional meshes, with each inner node having 4 neighbors, is investigated. It is assumed that some nodes/links...
Lev Zakrevski, Mark G. Karpovsky
ICDCS
1996
IEEE
14 years 19 days ago
The Performance Value of Shared Network Caches in Clustered Multiprocessor Workstations
This paper evaluates the bene t of adding a shared cache to the network interface as a means of improving the performance of networked workstations con gured as a distributed shar...
John K. Bennett, Katherine E. Fletcher, William Ev...