287 search results - page 54 / 58 » The Case for a Single-Chip Multiprocessor |
314
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GLVLSI
2011
IEEE
14 years 9 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
160
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DAC
2006
ACM
16 years 6 months ago
2006
ACM
Networks-on-Chip (NoC) architectures provide a scalable solution to on-chip communication problem but the bandwidth offered by NoCs can be utilized efficiently only in presence of...
156
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PPOPP
2010
ACM
16 years 16 days ago
2010
ACM
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
172
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LCTRTS
2010
Springer
16 years 16 days ago
2010
Springer
With increasingly more complex Multi-Processor Systems on Chip (MPSoC) and shortening time-to- market projections, Transaction Level Modeling and Platform Aware Design are seen as...
170
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VMCAI
2009
Springer
16 years 14 days ago
2009
Springer
There has been a lot of recent research on transaction-based concurrent programming, aimed at offering an easier concurrent programming paradigm that enables programmers to better...