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ACSD
2008
IEEE
135views Hardware» more  ACSD 2008»
13 years 8 months ago
Synthesis of Petri nets from infinite partial languages
In this paper we present an algorithm to synthesize a finite unlabeled place/transition Petri net (p/t-net) from a possibly infinite partial language, which is given by a term ove...
Robin Bergenthum, Jörg Desel, Robert Lorenz, ...
BCS
2008
13 years 8 months ago
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Pr...
Qiang Liu, George A. Constantinides, Konstantinos ...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 3 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ARC
2008
Springer
104views Hardware» more  ARC 2008»
13 years 8 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
PODC
2009
ACM
14 years 3 months ago
Memory models: a case for rethinking parallel languages and hardware
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
Sarita V. Adve