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HPCA
2012
IEEE
12 years 2 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...
ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
12 years 2 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
PADL
2012
Springer
12 years 2 months ago
Typing the Numeric Tower
In the past, the creators of numerical programs had to choose between simple expression of mathematical formulas and static type checking. While the Lisp family and its dynamically...
Vincent St-Amour, Sam Tobin-Hochstadt, Matthew Fla...
POPL
2012
ACM
12 years 2 months ago
The marriage of bisimulations and Kripke logical relations
There has been great progress in recent years on developing effective techniques for reasoning about program equivalence in ML-like languages—that is, languages that combine fea...
Chung-Kil Hur, Derek Dreyer, Georg Neis, Viktor Va...
STACS
2012
Springer
12 years 2 months ago
On Computing Pareto Stable Assignments
Assignment between two parties in a two-sided matching market has been one of the central questions studied in economics, due to its extensive applications, focusing on different...
Ning Chen