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» The Complexity of Planarity Testing
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ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 8 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
SMA
1999
ACM
107views Solid Modeling» more  SMA 1999»
15 years 8 months ago
Generation of swept volumes of toroidal endmills in five-axis motion using space curves
Accurate prediction of the swept volume of a cutting tool is essential in NC verification algorithms for detecting deficiencies in a proposed tool path, such as gouging, undercutt...
David Roth, Sanjeev Bedi, Fathy Ismail
VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
15 years 8 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
CADE
1998
Springer
15 years 8 months ago
System Description: leanK 2.0
Abstract. leanK is a "lean", i.e., extremely compact, Prolog implementation of a free variable tableau calculus for propositional modal logics. leanK 2.0 includes additio...
Bernhard Beckert, Rajeev Goré
AMOST
2007
ACM
15 years 7 months ago
Using LTL rewriting to improve the performance of model-checker based test-case generation
Model-checkers have recently been suggested for automated software test-case generation. Several works have presented methods that create efficient test-suites using model-checker...
Gordon Fraser, Franz Wotawa