74 search results - page 7 / 15 » The Cyclic Wirelength of Trees |
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
- In routing, finding a rectilinear Steiner minimal tree (RSMT) is a fundamental problem. Today's design often contains rectilinear obstacles, like macro cells, IP blocks, and...
LPAR
2001
Springer
14 years 2 months ago
2001
Springer
Several logic-based languages, such as Prolog II and its successors, SICStus Prolog and Oz, offer a computation domain including rational trees. Infinite rational trees allow fo...
ICFP
2008
ACM
14 years 9 months ago
2008
ACM
The Revised6 Report on Scheme requires its generic equivalence predicate, equal?, to terminate even on cyclic inputs. While the terminating equal? can be implemented via a DFA-equ...
DAC
2005
ACM
14 years 10 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
TCAD
2008
13 years 9 months ago
2008
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...