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HIPC
2004
Springer
14 years 2 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
CODES
2003
IEEE
14 years 2 months ago
RTOS scheduling in transaction level models
the level of abstraction in system design promises to enable faster exploration of the design space at early stages. While scheduling decision for embedded software has great impa...
Haobo Yu, Andreas Gerstlauer, Daniel Gajski
EH
2003
IEEE
117views Hardware» more  EH 2003»
14 years 2 months ago
The Evolutionary Design and Synthesis of Non-Linear Digital VLSI Systems
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
Robert Thomson, Tughrul Arslan
ICNP
2003
IEEE
14 years 2 months ago
The Impact of False Sharing on Shared Congestion Management
Several recent proposals for sharing congestion information across concurrent flows between end-systems overlook an important problem: two or more flows sharing congestion state...
Aditya Akella, Srinivasan Seshan, Hari Balakrishna...
ICNP
2003
IEEE
14 years 2 months ago
Characterizing Overlay Multicast Networks
Overlay networks among cooperating hosts have recently emerged as a viable solution to several challenging problems, including multicasting, routing, content distribution, and pee...
Sonia Fahmy, Minseok Kwon