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GLVLSI
2008
IEEE
147views VLSI» more  GLVLSI 2008»
14 years 2 months ago
Statistical timing analysis of flip-flops considering codependent setup and hold times
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
Safar Hatami, Hamed Abrishami, Massoud Pedram
SOSP
2009
ACM
14 years 4 months ago
Debugging in the (very) large: ten years of implementation and experience
Windows Error Reporting (WER) is a distributed system that automates the processing of error reports coming from an installed base of a billion machines. WER has collected billion...
Kirk Glerum, Kinshuman Kinshumann, Steve Greenberg...
GLVLSI
2006
IEEE
152views VLSI» more  GLVLSI 2006»
14 years 1 months ago
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology
This paper introduces a standard cell based design for a Serializer and Deserializer (SerDes) communication link. The proposed design is area, power and design time efficient as c...
Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
WSCG
2004
154views more  WSCG 2004»
13 years 9 months ago
Emulating an Offline Renderer by 3D Graphics Hardware
3D design software has since long employed graphics chips for low-quality real-time previewing. But their dramatically increased computing power now paves the way to accelerate th...
Jörn Loviscach
SEM
2004
Springer
14 years 1 months ago
Accuracy of Performance Prediction for EJB Applications: A Statistical Analysis
Abstract. A challenging software engineering problem is the design and implementation of component-based (CB) applications that can meet specified performance requirements. Our PPC...
Yan Liu, Ian Gorton