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» The Design and Performance of a Conflict-Avoiding Cache
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ISCA
1998
IEEE
136views Hardware» more  ISCA 1998»
14 years 21 days ago
Exploiting Spatial Locality in Data Caches Using Spatial Footprints
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...
Sanjeev Kumar, Christopher B. Wilkerson
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
14 years 20 days ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...
ISVLSI
2007
IEEE
121views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Performance of Graceful Degradation for Cache Faults
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchit...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
IESS
2009
Springer
182views Hardware» more  IESS 2009»
13 years 6 months ago
Modeling Cache Effects at the Transaction Level
Abstract. Embedded system design complexities are growing exponentially. Demand has increased for modeling techniques that can provide both accurate measurements of delay and fast ...
Ardavan Pedram, David Craven, Andreas Gerstlauer
EUROSYS
2011
ACM
12 years 12 months ago
SRM-buffer: an OS buffer management technique to prevent last level cache from thrashing in multicores
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
Xiaoning Ding, Kaibo Wang, Xiaodong Zhang