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» The Design and Performance of a Conflict-Avoiding Cache
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ANCS
2009
ACM
13 years 6 months ago
Design and performance analysis of a DRAM-based statistics counter array architecture
The problem of maintaining efficiently a large number (say millions) of statistics counters that need to be updated at very high speeds (e.g. 40 Gb/s) has received considerable re...
Haiquan (Chuck) Zhao, Hao Wang, Bill Lin, Jun (Jim...
CAISE
1999
Springer
14 years 23 days ago
Design of Object Caching in a CORBA OTM System
Abstract. CORBA Object Transaction Monitors (OTM) refer to a middleware technology that enable the building of transactional, objectoriented information systems running in distribu...
Thomas Sandholm, Stefan Tai, Dirk Slama, Eamon Wal...
ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
14 years 2 months ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
DSD
2003
IEEE
107views Hardware» more  DSD 2003»
14 years 1 months ago
DYNORA: A New Caching Technique
Cache design for high performance computing requires the realization of two seemingly disjoint goals of higher hit ratios at reduced access times. Recent research advocates the us...
P. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran
SIGMETRICS
2005
ACM
14 years 2 months ago
The performance impact of kernel prefetching on buffer cache replacement algorithms
A fundamental challenge in improving the file system performance is to design effective block replacement algorithms to minimize buffer cache misses. Despite the well-known int...
Ali Raza Butt, Chris Gniady, Y. Charlie Hu