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» The Design and Performance of a Conflict-Avoiding Cache
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RTAS
2008
IEEE
16 years 13 days ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
DASFAA
2005
IEEE
154views Database» more  DASFAA 2005»
15 years 11 months ago
Mining Positive and Negative Association Rules from XML Query Patterns for Caching
Recently, several approaches that mine frequent XML query patterns and cache their results have been proposed to improve query response time. However, frequent XML query patterns m...
Ling Chen 0002, Sourav S. Bhowmick, Liang-Tien Chi...
WWW
2007
ACM
16 years 6 months ago
Consistency-preserving caching of dynamic database content
With the growing use of dynamic web content generated from relational databases, traditional caching solutions for throughput and latency improvements are ineffective. We describe...
Niraj Tolia, M. Satyanarayanan
ISLPED
2009
ACM
132views Hardware» more  ISLPED 2009»
16 years 17 days ago
Enabling ultra low voltage system operation by tolerating on-chip cache failures
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
CODES
2010
IEEE
15 years 4 months ago
Dynamic, non-linear cache architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, algorithm-heavy, memory-intensive applications that were originally designed and coded for generalpurpos...
Garo Bournoutian, Alex Orailoglu