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INFOCOM
1999
IEEE
14 years 22 days ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. ...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da...
SBACPAD
2003
IEEE
135views Hardware» more  SBACPAD 2003»
14 years 1 months ago
Adaptive Compressed Caching: Design and Implementation
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
Rodrigo S. de Castro, Alair Pereira do Lago, Dilma...
ISCA
2012
IEEE
333views Hardware» more  ISCA 2012»
11 years 11 months ago
Reducing memory reference energy with opportunistic virtual caching
Most modern cores perform a highly-associative translation look aside buffer (TLB) lookup on every memory access. These designs often hide the TLB lookup latency by overlapping it...
Arkaprava Basu, Mark D. Hill, Michael M. Swift
DASFAA
2007
IEEE
141views Database» more  DASFAA 2007»
14 years 2 months ago
CST-Trees: Cache Sensitive T-Trees
Abstract. Researchers have modified existing index structures into ones optimized for CPU cache performance in main memory database environments. A Cache Sensitive B+-Tree is one o...
Ig-hoon Lee, Junho Shim, Sang-goo Lee, Jonghoon Ch...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
14 years 2 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah