1493 search results - page 284 / 299 » The Design of a Parallel Graphics Interface |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
PDCAT
2009
Springer
14 years 1 months ago
2009
Springer
Abstract—In this paper, a tool named CheCUDA is designed to checkpoint CUDA applications that use GPUs as accelerators. As existing checkpoint/restart implementations do not supp...
ISORC
2002
IEEE
14 years 10 days ago
2002
IEEE
Object-oriented, concurrent, and event-based programming models provide a natural framework in which to express the behavior of distributed and embedded software systems. However,...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
CCR
2008
13 years 7 months ago
2008
Current network protocols must comply with rigid interfaces and rules of behavior to fit into well defined, vertical protocol stacks. It is difficult for network designers to offe...