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» The Energy Efficiency of IRAM Architectures
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TPDS
2002
105views more  TPDS 2002»
13 years 7 months ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
BROADNETS
2006
IEEE
13 years 9 months ago
Multicasting in Energy Aware Mobile Backbone Based Wireless Ad Hoc Networks
Multicast protocols for MANET typically construct a tree or mesh structure for multicast message distribution. Typical implementations impose scalability and efficiency limitation...
Choo-Chin Tan, Izhak Rubin
ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 4 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
DAC
2009
ACM
14 years 8 months ago
An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems
? In this paper we propose an adaptive scheduling and voltage/frequency selection algorithm which targets at energy harvesting systems. The proposed algorithm adjusts the processor...
Shaobo Liu, Qing Wu, Qinru Qiu
ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
13 years 11 months ago
Analytical energy dissipation models for low-power caches
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run tim...
Milind B. Kamble, Kanad Ghose