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» The Energy Efficiency of IRAM Architectures
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CODES
2006
IEEE
14 years 1 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
HPCA
2006
IEEE
14 years 1 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
ICDCS
2007
IEEE
13 years 11 months ago
uSense: A Unified Asymmetric Sensing Coverage Architecture for Wireless Sensor Networks
As a key approach to achieve energy efficiency in sensor networks, sensing coverage has been studied extensively. Researchers have designed many coverage protocols to provide vario...
Yu Gu, Joengmin Hwang, Tian He, David Hung-Chang D...
LCN
2005
IEEE
14 years 1 months ago
Data Dissemination based on Mobile Agent in Wireless Sensor Networks
Recently, mobile agents have been proposed for efficient data dissemination in sensor networks [1-6]. In the traditional client/server-based computing architecture, data at multip...
Min Chen, Taekyoung Kwon, Yanghee Choi
ICS
2010
Tsinghua U.
13 years 10 months ago
The auction: optimizing banks usage in Non-Uniform Cache Architectures
The growing influence of wire delay in cache design has meant that access latencies to last-level cache banks are no longer constant. Non-Uniform Cache Architectures (NUCAs) have ...
Javier Lira, Carlos Molina, Antonio Gonzále...