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» The Fail-Heterogeneous Architectural Model
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DAC
2005
ACM
16 years 5 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
DAC
2006
ACM
16 years 5 months ago
Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...
Wei-Shen Wang, Vladik Kreinovich, Michael Orshansk...
DAC
2006
ACM
16 years 5 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
SIGSOFT
2007
ACM
16 years 4 months ago
CTG: a connectivity trace generator for testing the performance of opportunistic mobile systems
The testing of the performance of opportunistic communication protocols and applications is usually done through simulation as i) deployments are expensive and should be left to t...
Roberta Calegari, Mirco Musolesi, Franco Raimondi,...
WWW
2008
ACM
16 years 4 months ago
Sewnet -: a framework for creating services utilizing telecom functionality
With Telecom market reaching saturation in many geographies and revenues from voice calls decreasing, Telecom operators are trying to identify new sources of revenue. For this pur...
Sumit Mittal, Dipanjan Chakraborty, Sunil Goyal, S...
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