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ISPASS
2005
IEEE
14 years 1 months ago
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestam...
Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste A...
MOBIDE
1999
ACM
14 years 8 hour ago
Accelerating Telnet Performance in Wireless Networks
This paper describes the design of a system that significantly improves the performance of telnet data delivery for 3270 and 5250 emulation so that access to legacy applications v...
Barron C. Housel, Ian Shields
IISWC
2008
IEEE
14 years 2 months ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
SAC
2009
ACM
14 years 2 months ago
Impact of NVRAM write cache for file system metadata on I/O performance in embedded systems
File systems make use of part of DRAM as the buffer cache to enhance its performance in traditional systems. In this paper, we consider the use of Non-Volatile RAM (NVRAM) as a w...
In Hwan Doh, Hyo J. Lee, Young Je Moon, Eunsam Kim...
TVLSI
2008
157views more  TVLSI 2008»
13 years 7 months ago
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...
Hyuk-Jun Lee, Eui-Young Chung