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ISLPED
2006
ACM
109views Hardware» more  ISLPED 2006»
14 years 1 months ago
Power reduction of multiple disks using dynamic cache resizing and speed control
This paper presents an energy-conservation method for multiple disks and their cache memory. Our method periodically resizes the cache memory and controls the rotation speeds unde...
Le Cai, Yung-Hsiang Lu
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 2 months ago
Operating System Controlled Processor-Memory Bus Encryption
—Unencrypted data appearing on the processor– memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Al...
Xi Chen, Robert P. Dick, Alok N. Choudhary
PVLDB
2008
96views more  PVLDB 2008»
13 years 7 months ago
H-store: a high-performance, distributed main memory transaction processing system
Our previous work has shown that architectural and application shifts have resulted in modern OLTP databases increasingly falling short of optimal performance [10]. In particular,...
Robert Kallman, Hideaki Kimura, Jonathan Natkins, ...
LCTRTS
2010
Springer
14 years 2 months ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
IPPS
2003
IEEE
14 years 1 months ago
Optimizing Synchronization Operations for Remote Memory Communication Systems
Synchronization operations, such as fence and locking, are used in many parallel operations accessing shared memory. However, a process which is blocked waiting for a fence operat...
Darius Buntinas, Amina Saify, Dhabaleswar K. Panda...