Sciweavers

6171 search results - page 1114 / 1235
» The FrameNet Data and Software
Sort
View
WSC
1997
13 years 9 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
FTCS
1996
110views more  FTCS 1996»
13 years 9 months ago
Experimental Assessment of Parallel Systems
In the research reported in this paper, transient faults were injected in the nodes and in the communication subsystem (by using software fault injection) of a commercial parallel...
João Gabriel Silva, Joao Carreira, Henrique...
PPSC
1993
13 years 9 months ago
I/O for TFLOPS Supercomputers
Scalable parallel computers with TFLOPS (Trillion FLoating Point Operations Per Second) performance levels are now under construction. While we believe TFLOPS processor technology...
Erik DeBenedictis, Stephen C. Johnson
NIPS
1992
13 years 9 months ago
Silicon Auditory Processors as Computer Peripherals
Several research groups are implementing analog integrated circuit models of biological auditory processing. The outputs of these circuit models have taken several forms, includin...
John Lazzaro, John Wawrzynek, Misha Mahowald, Mass...
WCE
2007
13 years 9 months ago
Metaplanning Model Based in an Organizational Memory
— When problems are present in production, equipment or the process which are critical for organizations, many management personnel and experts have to meet to propose a solution...
José Bernardo Parra Victorino, Raúl ...
« Prev « First page 1114 / 1235 Last » Next »