Hardware trends suggest that large-scale CMP architectures, with tens to hundreds of processing cores on a single piece of silicon, are iminent within the next decade. While exist...
Bratin Saha, Ali-Reza Adl-Tabatabai, Anwar M. Ghul...
Existing software thread integration (STI) methods provide synchronous thread progress within integrated functions. For the remaining, non-integrated portions of the secondary (or...
Nagendra J. Kumar, Siddhartha Shivshankar, Alexand...
The University Class Scheduler (UCS) presented in this paper is a novel scheduling tool intended to be used by universities to schedule classes into classrooms. In essence, UCS al...
Deanna M. Needell, Jeff A. Stuart, Tamara C. Thiel...
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
This paper presents a hardware/software co-design for Multi Protocol Label Switching (MPLS) using RSVP-TE as a signaling protocol. MPLS is the protocol framework on which the atte...