4015 search results - page 753 / 803 » The Future of Software Performance Engineering |
144
click to vote
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a dynamic optimization technique, thread warping, that uses a single processor on a multiprocessor system to dynamically synthesize threads into custom accelerator circ...
145
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
Memory requirements of intellectual property components (IP) in contemporary multi-processor systems-on-chip are increasing. Large high-speed external memories, such as DDR2 SDRAM...
123
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
In battery-powered embedded systems, dedicated circuitry is used to convert stored energy into a form that can be directly used by processors. These power regulation devices seek ...
130
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper we present an approach to the scheduling and voltage scaling of low-power fault-tolerant hard real-time applications mapped on distributed heterogeneous embedded sys...
129
click to vote
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...