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PPOPP
2010
ACM
14 years 4 months ago
Data transformations enabling loop vectorization on multithreaded data parallel architectures
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrig...
EPS
1995
Springer
13 years 10 months ago
PANIC: A Parallel Evolutionary Rule Based System
PANIC (Parallelism And Neural networks In Classifier systems) is a parallel system to evolve behavioral strategies codified by sets of rules. It integrates several adaptive techni...
Antonella Giani, Fabrizio Baiardi, Antonina Starit...
HPDC
2010
IEEE
13 years 7 months ago
Parallel processing of data from very large-scale wireless sensor networks
In this paper we explore the problems of storing and reasoning about data collected from very large-scale wireless sensor networks (WSNs). Potential worldwide deployment of WSNs f...
Christine Jardak, Janne Riihijärvi, Frank Old...
IJCNN
2007
IEEE
14 years 1 months ago
Implementation of multi-layer leaky integrator networks on a cellular processor array
- We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motiva...
David R. W. Barr, Piotr Dudek, Jonathan M. Chamber...
HIPC
2009
Springer
13 years 4 months ago
A performance prediction model for the CUDA GPGPU platform
The significant growth in computational power of modern Graphics Processing Units(GPUs) coupled with the advent of general purpose programming environments like NVIDA's CUDA,...
Kishore Kothapalli, Rishabh Mukherjee, M. Suhail R...