2424 search results - page 187 / 485 » The High Level Architecture for Simulations |
162
click to vote
GLVLSI
2007
IEEE
15 years 7 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
141
click to vote
BMCBI
2006
15 years 6 months ago
2006
Background: Microarray technologies have become common tools in biological research. As a result, a need for effective computational methods for data analysis has emerged. Numerou...
150
click to vote
BMCBI
2010
15 years 6 months ago
2010
Background: Probing the complex fusion of genetic and environmental interactions, metabolic profiling (or metabolomics/metabonomics), the study of small molecules involved in meta...
148
click to vote
DAC
1995
ACM
15 years 9 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
146
click to vote
VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
Embedded DRAM (eDRAM) power-energy estimation is presented for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improve...