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» The High Level Architecture for Simulations
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IPPS
2010
IEEE
15 years 4 months ago
Acceleration of spiking neural networks in emerging multi-core and GPU architectures
Recently, there has been strong interest in large-scale simulations of biological spiking neural networks (SNN) to model the human brain mechanisms and capture its inference capabi...
Mohammad A. Bhuiyan, Vivek K. Pallipuram, Melissa ...
176
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INFOCOM
2003
IEEE
15 years 11 months ago
Distributed Admission Control to Support Guaranteed Services in Core-Stateless Networks
— The core-stateless service architecture alleviates the scalability problems of the integrated service framework while maintaining its guaranteed service semantics. The admissio...
Sudeept Bhatnagar, B. R. Badrinath
DSD
2006
IEEE
135views Hardware» more  DSD 2006»
15 years 9 months ago
Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography
Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this ...
Jacques J. A. Fournier, Simon W. Moore
SIGARCH
2008
97views more  SIGARCH 2008»
15 years 6 months ago
SP-NUCA: a cost effective dynamic non-uniform cache architecture
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
Javier Merino, Valentin Puente, Pablo Prieto, Jos&...
JPDC
2007
167views more  JPDC 2007»
15 years 6 months ago
On the design of high-performance algorithms for aligning multiple protein sequences on mesh-based multiprocessor architectures
In this paper, we address the problem of multiple sequence alignment (MSA) for handling very large number of proteins sequences on mesh-based multiprocessor architectures. As the ...
Diana H. P. Low, Bharadwaj Veeravalli, David A. Ba...