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» The High Level Architecture for Simulations
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TVLSI
2010
13 years 3 months ago
Asynchronous Current Mode Serial Communication
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...
Rostislav (Reuven) Dobkin, Michael Moyal, Avinoam ...
BMCBI
2011
13 years 6 days ago
Learning sparse models for a dynamic Bayesian network classifier of protein secondary structure
Background: Protein secondary structure prediction provides insight into protein function and is a valuable preliminary step for predicting the 3D structure of a protein. Dynamic ...
Zafer Aydin, Ajit Singh, Jeff Bilmes, William Staf...
CODES
2011
IEEE
12 years 8 months ago
DistRM: distributed resource management for on-chip many-core systems
The trend towards many-core systems comes with various issues, among them their highly dynamic and non-predictable workloads. Hence, new paradigms for managing resources of many-c...
Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfg...
TON
2012
11 years 11 months ago
A Transport Protocol to Exploit Multipath Diversity in Wireless Networks
Abstract—Wireless networks (including wireless mesh networks) provide opportunities for using multiple paths. Multihoming of hosts, possibly using different technologies and prov...
Vicky Sharma, Koushik Kar, K. K. Ramakrishnan, Shi...
BMCBI
2006
156views more  BMCBI 2006»
13 years 8 months ago
Bayesian models for pooling microarray studies with multiple sources of replications
Background: Biologists often conduct multiple but different cDNA microarray studies that all target the same biological system or pathway. Within each study, replicate slides with...
Erin M. Conlon, Joon J. Song, Jun S. Liu