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ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
14 years 1 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
13 years 14 days ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
ICPP
2008
IEEE
14 years 3 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
EGITALY
2006
13 years 10 months ago
Recovering 3D architectural information from dense digital models of buildings
In recent years the progress of 3D scanning technologies and the consequent growing commercialization of scanners opened a large spectrum of opportunities for many professionals. ...
A. Spinelli, Fabio Ganovelli, Claudio Montani, Rob...
WSC
1998
13 years 10 months ago
Communication Mission-type Orders to Virtual Commanders
This paper discusses issues in modeling C4I and cognitive processes in next generation simulations and applications to Force XXI command and control. We propose a modification to ...
Martin S. Kleiner, Scott A. Carey, Joseph E. Beach