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» The High Level Architecture for Simulations
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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 5 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
DSRT
1999
IEEE
14 years 1 months ago
Collaborative Virtual Environment Standards: A Performance Evaluation
Collaborative Virtual Environments are virtual reality spaces that enable participants to collaborate and share objects as if physically present in the same place. These collabora...
Jauvane C. de Oliveira, Shervin Shirmohammadi, Nic...
KBS
2002
69views more  KBS 2002»
13 years 8 months ago
A knowledge-based approach for business process reengineering, SHAMASH
In this paper we present an overview of SHAMASH, a process modelling tool for business process reengineering. The main features that differentiate it from most current related too...
Ricardo Aler, Daniel Borrajo, David Camacho, Almud...
CAMP
2005
IEEE
14 years 2 months ago
Development of a Bit-Level Compiler for Massively Parallel Vision Chips
Abstract— An image sensor in which each pixel has a processing element is called a vision chip. The vision chip can perform real-time visual processing at a high frame rate of 10...
Takashi Komuro, Shingo Kagami, Masatoshi Ishikawa,...
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 5 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...