2424 search results - page 82 / 485 » The High Level Architecture for Simulations |
FPGA
1999
ACM
14 years 1 months ago
1999
ACM
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
GLVLSI
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
ICMCS
2005
IEEE
14 years 2 months ago
2005
IEEE
In this research, an architecture that performs both forward and inverse lifting-based discrete wavelet transform is proposed. The proposed architecture reduces the hardware requi...
ASPLOS
1998
ACM
14 years 1 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
DAC
1997
ACM
14 years 1 months ago
1997
ACM
The design process for xed-point implementations either in software or in hardware requires a bit-true speci cation of the algorithm in order to analyze quantization e ects on an...