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CHES
2009
Springer
137views Cryptology» more  CHES 2009»
14 years 8 months ago
Faster and Timing-Attack Resistant AES-GCM
We present a bitsliced implementation of AES encryption in counter mode for 64-bit Intel processors. Running at 7.59 cycles/byte on a Core 2, it is up to 25% faster than previous i...
Emilia Käsper, Peter Schwabe
APWEB
2005
Springer
14 years 1 months ago
DSL Weaving for Distributed Information Flow Systems
Aspect-oriented programming (AOP) is a promising field for reducing application complexity. However, it has proven difficult to implement weavers for general purpose languages. Nev...
Calton Pu, Galen S. Swint
ISCA
2003
IEEE
96views Hardware» more  ISCA 2003»
14 years 1 months ago
Parallelism in the Front-End
As processor back-ends get more aggressive, front-ends will have to scale as well. Although the back-ends of superscalar processors have continued to become more parallel, the fro...
Paramjit S. Oberoi, Gurindar S. Sohi
ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
13 years 12 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
ASPLOS
2004
ACM
14 years 1 months ago
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...