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EUROMICRO
1999
IEEE
14 years 19 hour ago
Delft-Java Dynamic Translation
This paper describes the DELFT-JAVA processor and the mechanisms required to dynamically translate JVM instructions into DELFT-JAVA instructions. Using a form of hardware register...
C. John Glossner, Stamatis Vassiliadis
HICSS
1997
IEEE
90views Biometrics» more  HICSS 1997»
13 years 12 months ago
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors
We describe an environment to produce traces representing significant workloads for a shared-bus shared-memory multiprocessor used as a general-purpose multitasking machine, wher...
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Pr...
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
13 years 12 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
ASPDAC
2007
ACM
135views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Architectural Optimizations for Text to Speech Synthesis in Embedded Systems
Abstract-- The increasing processing power of embedded devices have created the scope for certain applications that could previously be executed in desktop environments only, to mi...
Soumyajit Dey, Monu Kedia, Anupam Basu
HIPEAC
2009
Springer
13 years 11 months ago
MPSoC Design Using Application-Specific Architecturally Visible Communication
Abstract. This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide highthroughput communication for str...
Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo ...