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SC
2009
ACM
14 years 2 months ago
Future scaling of processor-memory interfaces
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis,...
RV
2010
Springer
104views Hardware» more  RV 2010»
13 years 6 months ago
StealthWorks: Emulating Memory Errors
A study of Google’s data center revealed that the incidence of main memory errors is surprisingly high. These errors can lead to application and system corruption, impacting reli...
Musfiq Rahman, Bruce R. Childers, Sangyeun Cho
LCTRTS
2010
Springer
14 years 2 months ago
Versatile system-level memory-aware platform description approach for embedded MPSoCs
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
Robert Pyka, Felipe Klein, Peter Marwedel, Stylian...
HIPS
1997
IEEE
14 years 7 days ago
Complexity and Performance in Parallel Programming Languages
Several parallel programming languages, libraries and environments have been developed to ease the task of writing programs for multiprocessors. Proponents of each approach often ...
Steven P. Vanderwiel, Daphna Nathanson, David J. L...
ISCA
1992
IEEE
111views Hardware» more  ISCA 1992»
14 years 2 days ago
Lazy Release Consistency for Software Distributed Shared Memory
Relaxed memory consistency models, such as release consistency, were introduced in order to reduce the impact of remote memory access latency in both software and hardware distrib...
Peter J. Keleher, Alan L. Cox, Willy Zwaenepoel