202 search results - page 11 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
SAMOS
2007
Springer
14 years 1 months ago
2007
Springer
Abstract—Most research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a wor...
ICMCS
2006
IEEE
14 years 1 months ago
2006
IEEE
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
MICRO
2002
IEEE
14 years 14 days ago
2002
IEEE
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
CJ
2006
13 years 7 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...