202 search results - page 17 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ICS
2000
Tsinghua U.
14 years 9 days ago
2000
Tsinghua U.
One of the main concerns in today's processor design is the issue logic. Instruction-level parallelism is usually favored by an out-of-order issue mechanism where instruction...
ENTCS
2007
13 years 8 months ago
2007
Performance prediction methods for component-based software systems aim at supporting design decisions of software architects during early development stages. With the increased a...
DAC
2012
ACM
11 years 11 months ago
2012
ACM
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
MICRO
1994
IEEE
14 years 25 days ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...