202 search results - page 24 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
As the web becomes the platform of choice for execution of more complex applications, a growing portion of computation is handed off by developers to the client side to reduce net...
PACT
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
— Security is emerging as an important concern in embedded system design. The security of embedded systems is often compromised due to vulnerabilities in “trusted” software t...
IEEEPACT
2003
IEEE
14 years 25 days ago
2003
IEEE
Simultaneous multithreading (SMT) increases processor throughput by multiplexing resources among several threads. Despite the commercial availability of SMT processors, several as...