202 search results - page 26 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
183
Voted
ISVLSI
2005
IEEE
16 years 1 months ago
2005
IEEE
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate...
201
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APCSAC
2005
IEEE
16 years 1 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
196
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DFT
2003
IEEE
16 years 23 days ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
205
Voted
ASPLOS
2004
ACM
16 years 27 days ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
251
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APCSAC
2007
IEEE
16 years 1 months ago
2007
IEEE
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...