202 search results - page 26 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate...
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...
DFT
2003
IEEE
14 years 26 days ago
2003
IEEE
This paper presents an approach for integrating fault-tolerance techniques into microprocessors by utilizing instruction redundancy as well as time redundancy. Smaller and smaller...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
APCSAC
2007
IEEE
14 years 1 months ago
2007
IEEE
Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of...