202 search results - page 27 / 41 » The Instruction Execution Mechanism for Responsive Multithre... |
CGO
2009
IEEE
14 years 2 months ago
2009
IEEE
The development of high-performance libraries has become extraordinarily difficult due to multiple processor cores, vector instruction sets, and deep memory hierarchies. Often, t...
MST
2002
13 years 7 months ago
2002
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
RENO is a modified MIPS R10000 register renamer that uses map-table “short-circuiting” to implement dynamic versions of several well-known static optimizations: move eliminat...
SBACPAD
2008
IEEE
14 years 1 months ago
2008
IEEE
The performance impact of the Physical Register File (PRF) size on Simultaneous Multithreading processors has not been extensively studied in spite of being a critical shared reso...
ASPLOS
2004
ACM
14 years 1 months ago
2004
ACM
Dynamic information flow tracking is a hardware mechanism to protect programs against malicious attacks by identifying spurious information flows and restricting the usage of sp...